In a standard digital and mixed-signal design, clock storage elements (CSE), such as flip-flops, latch circuits and registers, are required to be operated in synchrony with a reference clock signal (also called as a global clock signal). In synchronous system design, broadcasting the global clock signal in a clock network directly from its source to every clock storage element causes a significant fraction of dynamic power. In addition, it is hard to maintain quality of the original global clock signal during transmission over the clock network.
Distributed clock regenerator (DCR) is a technique that can improve performance, especially power reduction, of the clock network. Firstly, DCR provides gain to drive corresponding clock storage elements, such that a loading of the global clock source can be reduced. Secondly, DCR provides a clock gating function, which is configured to activate a local clock signal for clock storage elements in use and to deactivate the local clock signal for other idling clock storage elements. In addition, some DCRs also provide functions for testing.
In some practical applications, some control signals (e.g., a test-hold signal and a scan enable signal for testing purposes, and a clock-gating signal for power saving purposes) are utilized to determine whether the local clock signal is generated or not by the DCR. The setup time of these control signals (especially for the clock-gating signal) is usually tighter than other signals on a data path. A critical path affecting a cycling time involving the DCR usually involves the clock-gating signal, because the clock-gating signal is typically generated by complex logic circuits.